1. Field of the Invention
The invention relates generally to memory systems, and more particularly to systems and methods for reducing the capacitance associated with certain memory systems thereby increasing the speed with which memory cells can be read and reducing the power required by the memory system.
2. Related Art
There is a continuing demand in the design of electronic circuits for increased computational power and decreased size and power consumption. These goals are achieved in various ways, such as by improving the physical characteristics of the devices. For example, computational power may be increased by developing components that can operate at higher clock speeds than previous components. Device size may be reduced by using technologies that allow smaller features to be constructed on an integrated circuit die. Lower power consumption may be achieved by using lower power supply voltages. Many other techniques are also used to meet these demands.
There are, however, physical limitations to some of these techniques. For instance, the frequency of the clock signal used in a digital circuit cannot be increased beyond the point at which the components that use the clock signal become unstable. Similarly, a power supply voltage cannot be reduced to a level at which the components operating on this supply voltage no longer function properly, and the physical size of a circuit components cannot be reduced to a size which is too small to be resolved using available process technologies. It is therefore necessary to find better ways to take advantage of the available technologies.
Once such way of taking advantage of available technologies in the context of memory devices is the use of a hierarchical bit line scheme to read SRAM memory cells. In a conventional system, many SRAM cells (see, e.g., 128 in FIG. 1) might be connected to a single, common bit line. Typically, there is a small amount of leakage current between each SRAM cell and the bit line. As a result of the current leaks in all of the cells connected to the bit line, it can be difficult to reliably read data from a single one of the cells. Hierarchical bit line schemes were developed to allow the SRAM cells to be grouped together in smaller numbers so that each cell could be reliably read, despite the leakage from the smaller number of cells.
In a conventional hierarchical bit line scheme, a first group of cells (16, for example) is coupled to a first bit line, while a second group of cells of the same number is coupled to a second bit line. Each of the bit lines is input to an evaluation circuit. The outputs of multiple evaluation circuits are then input to further evaluation circuitry. In this manner, a number of cells equivalent to a conventional system (e.g., 128 cells) can be read, even though the cells are grouped into smaller numbers (e.g., 16) on each common bit line.
Even this hierarchical bit line scheme can be improved, however. Because of the connections between metal traces that form the system and the close proximity of some of the traces in the conventional system, there is capacitance which reduces the maximum speed at which the cells can be operated and also increases the power required to operate the cells. Additionally, the vias that connect the traces may fail, causing the memory cells to fail.
It would therefore be desirable to configure the memory cells so that the capacitance in the memory cells is reduced, thereby increasing the speed at which the cells can be operated and reducing the power required by the cells. It would also be desirable to reduce failures in the vias, thereby increasing the yield of the memory cells.